1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to transistors having strained channel regions by using stress sources, such as stressed overlayers, a strained semiconductor alloy in drain and source areas to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced in the field of semiconductor production, wherein, for complex circuitry, such as microprocessors, complex storage chips and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length is a dominant design criterion for accomplishing an increase in the operating speed and packing density of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is to provide low sheet and contact resistivity in drain and source regions and any contacts connected thereto and to maintain channel controllability. For example, reducing the channel length may necessitate an increase of the capacitive coupling between the gate electrode and the channel region, which may call for reduced thickness of the gate insulation layer. Presently, the thickness of silicon dioxide based gate insulation layers is in the range of 1-2 nm, wherein a further reduction may be less desirable in view of leakage currents which typically exponentially increase when reducing the gate dielectric thickness.
The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified problems. It has, therefore, been proposed to improve transistor performance by enhancing the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential of achieving a performance improvement that is comparable with the advance to a future technology node, while avoiding or at least postponing many of the above-mentioned problems, such as gate dielectric scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance, by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, for standard silicon substrates, creating tensile strain in the channel region increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity and thus drive current and operating speed. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
According to one promising approach for creating strain in the channel region of transistor elements, the dielectric material that is formed above the basic transistor structure may be provided in a highly stressed state so as to induce a desired type of strain at the transistor and in particular in the channel region thereof. For example, the transistor structures are typically enclosed by an interlayer dielectric material, which may provide the desired mechanical and electrical integrity of the individual transistor structures and which may provide a platform for the formation of additional wiring layers, which are typically required for providing the electrical interconnections between the individual circuit elements. That is, a plurality of wiring levels or metallization layers may typically be provided which may include horizontal metal lines and vertical vias including appropriate conductive materials for establishing the electrical connections. Consequently, an appropriate contact structure has to be provided which connects the actual circuit elements, such as transistors, capacitors and the like, or respective portions thereof, with the very first metallization layer. For this purpose, the interlayer dielectric material has to be appropriately patterned in order to provide respective openings connecting to the desired contact areas of the circuit elements, which may typically be accomplished by using an etch stop material in combination with the actual interlayer dielectric material.
For example, silicon dioxide is a well-established interlayer dielectric material, in combination with silicon nitride, which may act as an efficient etch stop material during the formation of the contact openings. Consequently, the etch stop material, i.e., the silicon nitride material, is in close contact with the basic transistor structure and thus may be efficiently used for inducing strain in the transistors, in particular as silicon nitride may be deposited on the basis of well-established plasma enhanced chemical vapor deposition (CVD) techniques with high internal stress. For instance, silicon nitride may be deposited with high internal compressive stress of up to 2 GPa and even higher by selecting appropriate deposition parameters. On the other hand, a moderately high internal tensile stress level may be created to 1 GPa and higher by appropriately adjusting the process parameters, for instance, in particular, the degree of ion bombardment during the deposition of the silicon nitride material. Consequently, the magnitude of the strain created in the channel region of a transistor element may depend on the internal stress level of the dielectric etch stop material and the thickness of stressed dielectric material, in combination with the effective offset of the highly stressed dielectric material with respect to the channel region. Consequently, in view of enhancing transistor performance, it may be desirable to increase the internal stress level and also provide enhanced amounts of highly stressed dielectric material in the vicinity of the transistor element, while also positioning the stressed dielectric material as closely as possible to the channel region. It turns out, however, that the internal stress levels of silicon nitride material may be restricted by the overall deposition capabilities of presently available plasma enhanced CVD techniques, while the effective layer thickness may also be substantially determined by the basic transistor topography and the distance between neighboring circuit elements. Consequently, although providing significant advantages, the efficiency of the stress transfer mechanism may significantly depend on process and device specifics and may result in reduced performance gain for well-established standard transistor designs having gate lengths of 50 nm and less, since the given device topography and the gap fill capabilities of the respective deposition process, in combination with a moderately high offset of the highly stressed material from the channel region caused by sophisticated spacer structures, may reduce the finally obtained strain in the channel region.
For these reasons, it has also been suggested to improve performance of transistors, such as P-channel transistors, by providing semiconductor materials, at least in portions of the drain and source areas, in such a manner that a desired type of strain may be generated in the adjacent channel region. For this purpose, frequently, a silicon/germanium mixture or alloy may be used, which may be grown by selective epitaxial growth techniques on a silicon template material, thereby creating a strained state of the silicon/germanium alloy, which may exert a certain stress on the adjacent channel region, thereby creating the desired type of strain therein. Consequently, in combination with an overlying stressed dielectric material, a highly efficient strain-inducing mechanism may be accomplished for P-channel transistors.
As previously discussed, in sophisticated transistor elements, a plurality of features finally determine the overall performance of the transistor, wherein a complex mutual interaction of these factors may be difficult to assess so that a wide variety of performance variations may be observed for a given basic transistor configuration. For example, the conductivity of doped silicon-based semiconductor regions may be increased by providing a metal silicide therein in order to reduce overall sheet resistance and contact resistivity. For example, the drain and source regions may receive a metal silicide, such as nickel silicide, nickel platinum silicide and the like, thereby reducing the overall series resistance of the conductive path between the drain and source terminals and the intermediate channel region. Similarly, a metal silicide may typically be formed in the gate electrode, which may comprise polysilicon material, thereby enhancing conductivity and thus reducing signal propagation delay. Although an increased amount of metal silicide in the gate electrode may per se be desirable in view of reducing the overall resistance thereof, a substantially complete silicidation of the polycrystalline silicon material down to the gate dielectric material may not be desirable in view of threshold voltage adjustment of the corresponding transistor element. It may, therefore, be desirable to maintain a certain portion of the doped polysilicon material in direct contact with the gate dielectric material to provide well-defined electronic characteristics in the channel region, so as to avoid significant threshold variations, which may be caused by a substantially full silicidation within portions of the gate electrode. Consequently, it may be difficult to provide a significant amount of metal silicide, while nevertheless reliably avoiding a complete silicidation of the polysilicon material.
Other characteristics of the gate electrode may also have an influence on the overall transistor performance. For example, for continuously decreasing feature sizes of the transistor elements, it would be desirable to also reduce the height of the gate electrode, which, however, may typically be limited due to required ion blocking capabilities during the generation of the drain and source dopant profiles by sophisticated implantation techniques. This required gate height, however, may result in an increased fringing capacitance with respect to contact elements, which may be formed so as to connect the drain and source regions. Consequently, the overall performance of complex transistor elements may be less pronounced than expected, even though corresponding performance increasing mechanisms, such as strained silicon/germanium material and the like, may be used, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is formed a semiconductor layer 103, in which a plurality of isolation structures 104 may define active regions 103A, 103B of an N-channel transistor 150A and a P-channel transistor 150B, respectively. An active region is to be understood as a portion of the semiconductor layer 103 in which appropriate dopant profiles are to be established in order to obtain the desired transistor function. In the manufacturing stage shown, the transistors 150A, 150B comprise a gate electrode 151 that is formed on a gate insulation layer 152, which separates the gate electrode 151 from a channel region 153. Furthermore, a spacer structure 155 is formed on a portion of the sidewalls of the gate electrode 151, wherein it should be appreciated that the spacer structure 155 may have any appropriate configuration as is required for defining the dopant profile of corresponding drain and source regions 154. For example, the spacer structure 155 may comprise a plurality of individual spacer elements, possibly in combination with corresponding etch stop liners (not shown). As previously discussed, the P-channel transistor 150B comprises a silicon/germanium alloy 105, which may have a strained state so as to create a corresponding compressive strain component in the channel region 153 of the transistor 150B.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following process sequence. After forming the isolation structures 104, for instance by lithography, etch, deposition and planarization techniques, the active regions 103A, 103B may be defined by established implantation techniques in combination with a corresponding masking regime. Thereafter, the gate electrodes 151, in combination with the gate insulation layers 152, may be formed, for instance, providing an appropriate dielectric material and depositing a polysilicon material, which may then be patterned on the basis of sophisticated lithography and etch techniques. As previously explained, a height 151H of the gate electrode 151 may typically be selected to provide a sufficient ion blocking effect during the subsequent processing of the device 100. Thereafter, the transistor 150A may be masked, for instance by a hard mask in combination with a resist mask, while also the gate electrode 151 of the transistor 150B may be encapsulated, for instance on the basis of appropriate cap layers and sidewalls spacers (not shown) in order to form corresponding cavities in the active region 103B and subsequently depositing the silicon/germanium alloy 105 on the basis of selective epitaxial growth techniques. Next, the mask layer may be removed and the gate electrodes 151 may be exposed and the further processing may be continued, for instance by forming offset spacer elements, if required, which may be used for a first implantation sequence for defining a first part of the drain and source regions 154. Thereafter, the spacer structure 155 is formed by depositing an appropriate layer stack, such as an etch stop liner, such as silicon dioxide followed by a silicon nitride material, which may be accomplished by well-established CVD techniques. Thereafter, the layer stack is patterned by an anisotropic etch process, during which silicon nitride material is preferably removed from horizontal portions, while typically reliably exposing the horizontal device areas and also a portion 151S of the sidewalls of the gate electrodes 151 are exposed during the corresponding etch process and during subsequent etch and cleaning processes. Next, further implantation sequences may be performed so as to obtain the desired dopant profile for the drain and source regions 154. Thereafter, appropriate anneal processes are performed in order to activate the dopants and also re-crystallize implantation-induced damage. Thereafter, the device 100 is prepared for performing a silicidation process, which may typically include corresponding cleaning processes, thereby even further exposing the sidewall portion 151S.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which metal silicide regions 156 are formed in a portion of the drain and source regions 154, while also metal silicide 157 is formed in the gate electrode 151. In sophisticated technologies, frequently, nickel and platinum may be used for obtaining the metal silicide 156, 157 wherein, due to the different diffusion behavior of the polycrystalline material in the gate electrode 151 and the crystalline material in the drain and source regions 154, a significantly different “conversion rate” may be obtained, wherein, in particular at the sidewall portion 151 S, metal may increasingly diffuse into the gate electrode 151, thereby resulting in an increased silicidation rate. Consequently, the metal silicide 157 may extend down to the gate insulation layer 152, at least locally within the gate electrode 151, thereby resulting in a corresponding threshold voltage variation since the work function of the metal silicide may differ from the corresponding work function of the correspondingly doped polysilicon material. After the silicidation process, the further processing may be continued, for instance by depositing strain-inducing material layers, for instance in the form of silicon nitride, which may be deposited with high compressive and tensile stress, depending on the deposition parameters used. For example, a tensile stressed silicon nitride material may be formed above the N-channel transistor 150A, while a compressively stressed silicon nitride material may be formed above the transistor 150B, thereby appropriately enhancing overall performance of these transistors due to the corresponding additional strain created in the channel regions 153. Thereafter, an interlayer dielectric material, such as silicon dioxide and the like, is deposited and patterned so as to obtain corresponding contact openings, which are subsequently filled with a conductive material, such as tungsten, thereby providing contact elements connecting to the gate electrodes 151 and the drain and source regions 154. As previously discussed, the contact elements extending to the drain and source regions 154 may define, together with the gate electrode 151 and the intermediate dielectric material, a corresponding parasitic capacitor, which may have an influence on the overall channel controllability, which is typically referred to as fringing capacitance. Consequently, although reduced device dimensions may be applied in combination with sophisticated strain-inducing mechanisms, the transistors 150A, 150B may suffer from a less pronounced performance gain due to a moderately high fringing capacitance, while a certain degree of threshold variability may also be observed.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.